Principal ASIC Design Engineer

Job Description:
Principal ASIC Design Engineer
San Francisco · Full Time

Job Description

We are a small, fast-growing company looking to build out its Platform Engineering team to develop NPU IP and network appliances that will power our revolutionary application-defined networking ecosystem. As such, we are seeking an experienced ASIC or FPGA design engineer with significant understanding of L2 and L3 networking technology. The right candidate will be able to hit the ground running in developing major blocks in a complex FPGA SoC including writing specifications, designing micro-architecture, and coding RTL. As a small startup, our engineers play many roles so a proven track record in block-level verification and running backend synthesis and place-and-route tools is also a must.

Responsibilities

Contribute to overall architectural design of Bayware hardware products, focusing on chip-level requirements and hardware-software interaction
Write block-level specifications - excellent written communication skills expected
Design micro-architecture for FPGA blocks
Code Verilog and SystemVerilog RTL for design
Develop block-level verification environments
Run synthesis and place-and-route tools with ability to resolve timing and congestion issues as needed
Write scripts and bring-up software for lab debug

Required Skills

10+ years as ASIC/FPGA design engineer
Solid understanding of L2 and L3 networking protocols (10/40/100Gbps Ethernet, TCP/IP)
Microprocessor and/or PCIe design experience also a plus
Expert Verilog designer with strong interest in pushing what’s possible in silicon using latest tools and SystemVerilog constructs including assertions
Python, Perl, or shell scripting in Linux environment
C/C++ or other software experience preferred with understanding of common practices in developing hardware-software interfaces
Lab experience operating oscilloscopes, logic analyzers, traffic generators, etc. a plus

Education

BS or MS (preferred) in electrical or computer engineering with minimum 10 years relevant work experience

Compensation

$100K – $136K
No Equity
Visa Sponsorship
Not available

Kris Young
Account Director
BHO Tech
San Jose, San Francisco CA
Phone: (866) 816-1615 x 823
kris@bhotech.com
www.bhotech.com